Extended Receive Prescaler Division Register (Scierpr); Table 65. Receiver Rate Divider - STMicroelectronics ST72361 Auto Series Manual

LINSCI serial communication interface (LIN master/slave)
Table 64.
Bits 2:0 = SCR[2:0] SCI Receiver rate divider.
These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus
clock to yield the receive rate clock in conventional Baud Rate Generator mode.
Table 65.
15.8.6

Extended receive prescaler division register (SCIERPR)

Read/ write
Reset value: 0000 0000 (00h)
7
ERPR7
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register.
The extended baud rate generator is activated when a value other than 00h is stored in this
register. The clock frequency from the 16 divider (see
factor set in the SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
172/279
Transmitter rate divider
TR dividing factor
16
32
64
128
Receiver rate divider
RR dividing factor
1
2
4
8
16
32
64
128
ERPR6 ERPR5
Doc ID 12468 Rev 3
SCT2
1
SCR2
0
1
ERPR4 ERPR3
Figure
ST72361xx-Auto
SCT1 SCT0
0
1
SCR1 SCR0
0
1
0
1
ERPR2 ERPR1
79) is divided by the binary
0
1
0
1
0
1
0
1
0
1
0
1
0
ERPR0