Functional Description; Figure 70. Serial Peripheral Interface Block Diagram - STMicroelectronics ST72361 Auto Series Manual

Serial peripheral interface (SPI)

Figure 70. Serial peripheral interface block diagram

MOSI
MISO
SCK
SS
14.3.1

Functional description

A basic example of interconnections between a single master and a single slave is
illustrated in
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see
slave must be programmed with the same timing mode.
144/279
Data/Address Bus
Read
SPIDR
Read Buffer
8-Bit Shift Register
SOD
bit
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
Figure 71.
Doc ID 12468 Rev 3
7
SPIF WCOL
Write
7
SPIE SPE
ST72361xx-Auto
Interrupt
request
SPICSR
OVR MODF 0 SOD SSM
1
SS
SPI
0
STATE
CONTROL
SPICR
MSTR
SPR2 CPOL CPHA SPR1
Figure 74) but master and
0
SSI
0
SPR0