Baud Rate Register (Scibrr); Table 77. Pr Prescaler; Table 78. Transmitter Rate Divider - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto
16.8.6

Baud rate register (SCIBRR)

Read/ write
Reset value: 0000 0000 (00h)
7
SCP1
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges:
Table 77.
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division applied to
the bus clock to yield the transmit rate clock in conventional baud rate generator mode.
Table 78.
Note: This TR factor is used only when the ETPR fine tuning factor is equal to 00h; otherwise, TR
is replaced by the (TR*ETPR) dividing factor.
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division applied to
the bus clock to yield the receive rate clock in conventional baud rate generator mode.
LINSCI serial communication interface (LIN master only)
SCP0 SCT2
PR prescaler
PR prescaling factor
1
3
4
13
Transmitter rate divider
TR dividing factor
1
2
4
8
16
32
64
128
Doc ID 12468 Rev 3
SCT1 SCT0
SCP1
SCT2
0
1
SCR2 SCR1
SCP0
0
0
1
0
1
1
SCT1 SCT0
0
1
0
1
0
SCR0
0
1
0
1
0
1
0
1
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