Serial Peripheral Interface (Spi); Introduction; Main Features; General Description - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto
14

Serial peripheral interface (SPI)

14.1

Introduction

The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves or a
system in which devices may be either masters or slaves.
14.2

Main features

●
Full duplex synchronous transfers (on three lines)
●
Simplex synchronous transfers (on two lines)
●
Master or slave operation
● 6 master mode frequencies (f
●
f
CPU
● SS Management by software or hardware
●
Programmable clock polarity and phase
● End of transfer interrupt flag
●
Write collision, Master Mode Fault and Overrun flags
Note: In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
14.3

General description

Figure 70
registers:
● SPI Control Register (SPICR)
●
SPI Control/Status Register (SPICSR)
● SPI Data Register (SPIDR)
The SPI is connected to external devices through four pins:
●
MISO: Master In / Slave Out data
●
MOSI: Master Out / Slave In data
●
SCK: Serial Clock out by SPI masters and input by SPI slaves
●
SS: Slave select:
This input signal acts as a 'chip select' to let the SPI master communicate with slaves
individually and to avoid contention on the data lines. Slave SS inputs can be driven by
standard I/O ports on the master Device.
/2 max. slave mode frequency (see note)
shows the serial peripheral interface (SPI) block diagram. There are three
Doc ID 12468 Rev 3
/4 max.)
CPU
Serial peripheral interface (SPI)
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