Table 44. Pwm Frequency Vs Resolution - STMicroelectronics ST72361 Auto Series Manual

PWM auto-reload timer (ART)
Bit 0 = OVF Overflow Flag
This bit is set by hardware and cleared by software reading the ARTCSR register. It
indicates the transition of the counter from FFh to the ARTARR value
0: New transition not yet reached
1: Transition reached
Counter Access Register (ARTCAR)
Read/Write
Reset value: 0000 0000 (00h)
7
CA7
Bit 7:0 = CA[7:0] Counter Access Data
These bits can be set and cleared either by hardware or by software. The ARTCAR register
is used to read or write the auto-reload counter "on the fly" (while it is counting).
Auto-Reload Register (ARTARR)
Read/Write
Reset value: 0000 0000 (00h)
7
AR7
Bit 7:0 = AR[7:0] Counter Auto-Reload Data
These bits are set and cleared by software. They are used to hold the auto-reload value
which is automatically loaded in the counter when an overflow occurs. At the same time, the
PWM output levels are changed according to the corresponding OPx bit in the PWMCR
register.
This register has two PWM management functions:
●
Adjusting the PWM frequency
●
Setting the PWM duty cycle resolution
Table 44.
ARTARR value
[0..127]
[128..191]
[192..223]
[224..239]
98/279
CA6 CA5
AR6 AR5
PWM frequency vs resolution
Resolution
0
> 7-bit
> 6-bit
> 5-bit
> 4-bit
Doc ID 12468 Rev 3
CA4 CA3
AR4 AR3
8-bit ~0.244 kHz
~0.244 kHz
~0.488 kHz
~0.977 kHz
~1.953 kHz
ST72361xx-Auto
.
CA2 CA1
AR2 AR1
f
PWM
Min
31.25 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
0
CA0
0
AR0
Max