I/O Port Implementation; I/O Port Register Configurations; Standard Ports; Table 28. Configuration Of Pb7:6, Pc0, Pc3, Pc7:5, Pd3:2, Pd5, Pe7:0, Pf7:0 - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto
Warning:
8.3

I/O port implementation

The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.

Figure 33. Interrupt I/O port state transitions

8.4

I/O port register configurations

The I/O port register configurations are summarized as follows.
8.4.1

Standard ports

Table 28.
Floating input
Pull-up input
Open drain output
Push-pull output
The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
01
INPUT
floating/pull-up
interrupt
Configuration of PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0, PF7:0
Mode
Doc ID 12468 Rev 3
00 10
INPUT OUTPUT OUTPUT
floating open-drain push-pull
(reset state)
XX
= DDR, OR
Figure 33.
11
DDR OR
0
1
I/O ports
0
1
0
1
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