Control Pin Characteristics; Asynchronous Reset Pin; Table 107. Reset Pin Characteristics; Figure 111. Typical Voh Vs Vdd - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto
Figure 111. Typical V
6
5
4
3
2
19.10

Control pin characteristics

19.10.1

Asynchronous RESET pin

Subject to general operating conditions for V

Table 107. RESET pin characteristics

Symbol
V Input low level voltage
IL
V Input high level voltage
IH
Schmitt trigger voltage
V
hys
hysteresis
V Output low level voltage
OL
Weak pull-up equivalent
R
(4)
ON
resistor
t Generated reset pulse duration
w(RSTL)out
t External reset pulse hold time
h(RSTL)in
t Filtered glitch duration
g(RSTL)in
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I current sunk must always respect the absolute maximum rating specified in
IO
and the sum of I (I/O ports and control pins) must not exceed I
IO
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the
RESET pin with a duration below t
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy
environments.
6. Data guaranteed by design, not tested in production.
vs V
OH
3 4
Vdd(V)
Parameter
(1)
(1)
(2)
(3)
(5)
(6)
can be ignored.
h(RSTL)in
DD
6
5
4
-45°C
25°C
3
130°C
2
1
5 6 3
, f
DD OSC
Conditions
V = 5V
DD
I = +5mA
IO
V = 5V
DD
I = +2mA
IO
 V
V
IN SS
Internal reset source
.
VSS
Doc ID 12468 Rev 3
Electrical characteristics
-45°C
25°C
130°C
4 5
Vdd(V)
, and T unless otherwise specified.
A
Min Typ
0.7 x V
DD
1.5
0.68
0.28
20 40
30
2.5
200
Section 20.2.2: Current characteristics
6
Max Unit
0.3 x V
DD
V
0.95
0.45
80 k
µs
ns
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