Figure 30. Awuf Halt Timing Diagram; Figure 31. Awufh Mode Flow-Chart - STMicroelectronics ST72361 Auto Series Manual

Power saving modes

Figure 30. AWUF halt timing diagram

f
CPU
f
AWU_RC
AWUFH interrupt

Figure 31. AWUFH mode flow-chart

Note: 1 WDGHALT is an option bit. See option byte section for more details.
2 Peripheral clocked with an external clock source can still be active.
3 Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode
(such as external interrupt). Refer to
4 Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the
CC register are set to the current software priority level of the interrupt routine and
recovered when the CC register is popped.
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RUN MODE HALT MODE
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=1)
WDGHALT
1
WATCHDOG
RESET
N
INTERRUPT
Doc ID 12468 Rev 3
t
AWU
256 or 4096 t
ENABLE
WATCHDOG
0 DISABLE
1)
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
N
RESET
Y
3)
AWU RC OSC
Y MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
256 OR 4096 CPU CLOCK
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Table 16 for more details.
ST72361xx-Auto
RUN MODE
CPU
Clear
by software
ON
OFF
2)
OFF
OFF
10
OFF
ON
OFF
ON
4)
XX
OFF
ON
ON
ON
4)
XX