Summary Of Timer Modes; Register Description; Control Register 1 (Cr1); Table 49. Timer Modes - STMicroelectronics ST72361 Auto Series Manual

16-bit timer
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts
chapter). These events generate an interrupt if the corresponding Enable Control Bit is set
and the interrupt mask in the CC register is reset (RIM instruction).
12.6

Summary of timer modes

Table 49.
Modes
Input capture
(1 and/or 2)
Output compare
(1 and/or 2)
One pulse mode
PWM Mode
1. See note 4 in
2. See note 5 in
3. See note 4 in
12.7

Register description

Each Timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
12.7.1

Control register 1 (CR1)

Read/ write
Reset value: 0000 0000 (00h)
7
ICIE
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is
set.
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Timer modes
Input capture 1
Yes
No
One pulse mode
One pulse mode
Pulse width modulation mode
OCIE TOIE FOLV2
Doc ID 12468 Rev 3
Timer resources
Input capture 2 Output compare 1 Output compare 2
Yes
Not
(1)
recommended
Not
(3)
recommended
FOLV1
ST72361xx-Auto
Yes
Partially
No
OLVL2 IEDG1
Yes
(2)
No
0
OLVL1