Table 40. Cpu Clock Frequency In Slow Mode; Table 41. Time Base Selection - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto
Table 40.
f / 2
OSC2
f / 4
OSC2
f / 8
OSC2
f / 16
OSC2
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f
See Section 7.2: Slow mode
MCC/RTC
Bits 3:2 = TB[1:0] Time base control
These bits select the programmable divider time base. They are set and cleared by
software.
Table 41.
Counter prescaler
16000
32000
80000
200000
A modification of the time base is taken into account at the end of the current period
(previously set) to avoid an unwanted time shift. This allows to use this time base as a real
time clock.
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE HALT mode.
When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE HALT
power saving mode
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software reading the CSR register. It indicates
when set that the main oscillator has reached the selected elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CPU clock frequency in SLOW mode
f in SLOW mode
CPU
= f
CPU OSC2
is given by CP1, CP0
CPU
and
for more details.
Time base selection
f = 4 MHz
OSC2
4ms
8ms
20ms
50ms
.
Doc ID 12468 Rev 3
Main clock controller with real time clock MCC/RTC
Section 10: Main clock controller with real time clock
Time base
f
OSC2
2ms
4ms
10ms
25ms
CP1
0
1
TB1
= 8 MHz
0
1
CP0
0
1
0
1
TB0
0
1
0
1
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