ST72361xx-Auto
Figure 88. SCI block diagram
TDO
RDI
SCLK
16.4
Functional description
The block diagram of the serial control interface, is shown in
dedicated registers:
●
Three control registers (SCICR1, SCICR2 and SCICR3)
●
A status register (SCISR)
●
A baud rate register (SCIBRR)
●
An extended prescaler receiver register (SCIERPR)
●
An extended prescaler transmitter register (SCIETPR)
LINSCI serial communication interface (LIN master only)
Write
Transmit Data Register (TDR)
Transmit Shift Register
CLOCK EXTRACTION
PHASE AND POLARITY
CONTROL
TRANSMIT
CONTROL
SCICR2
TIE
TCIE
RIE
ILIE
TE
RE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
f
CPU
/PR
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Doc ID 12468 Rev 3
Read
Received Data Register (RDR)
Received Shift Register
LINE
-
-
CLKEN
CPOL CPHA LBCL
M
R8
T8
SCID
WAKE
WAKE
RECEIVER
UP
CONTROL
UNIT
TDRE TC RDRF IDLE OR
RWU
SBK
TRANSMITTER RATE
CONTROL
SCP1
SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
CONVENTIONAL BAUD RATE GENERATOR
(DATA REGISTER) SCIDR
SCICR3
SCICR1
PCE
PS
PIE
RECEIVER
CLOCK
SCISR
NF
FE
PE
SCIBRR
RECEIVER RATE
CONTROL
Figure
88. It contains seven
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