Linsci Clock Tolerance; Figure 84. Ldiv Read / Write Operations When Ldum = 0; Figure 85. Ldiv Read / Write Operations When Ldum = 1 - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto

Figure 84. LDIV read / write operations when LDUM = 0

Figure 85. LDIV read / write operations when LDUM = 1

15.9.7

LINSCI clock tolerance

LINSCI clock tolerance when unsynchronized
When LIN slaves are unsynchronized (meaning no characters have been transmitted for a
relatively long time), the maximum tolerated deviation of the LINSCI clock is +/-15%.
If the deviation is within this range then the LIN synch break is detected properly when a
new reception occurs.
This is made possible by the fact that masters send 13 low bits for the LIN synch break,
which can be interpreted as 11 low bits (13 bits -15% = 11.05) by a "fast" slave and then
considered as a LIN synch break. According to the LIN specification, a LIN synch break is
valid when its duration is greater than t
must last at least 11 low bits.
LINSCI serial communication interface (LIN master/slave)
Write LPFR
Write LPR
MANT(7:0) FRAC(3:0)
Write LPR
MANT(7:0) FRAC(3:0)
Read LPR Read LPFR
Write LPFR
Write LPR
MANT(7:0) FRAC(3:0)
RDRF = 1
MANT(7:0) FRAC(3:0)
Read LPR Read LPFR
Doc ID 12468 Rev 3
LDIV_NOM
MANT(7:0) FRAC(3:0)
Update
at end of
Synch Field
Baud Rate
LDIV
Generation
LDIV_NOM
MANT(7:0) FRAC(3:0)
Update
at end of
Synch Field
Baud Rate
LDIV
Generation
= 10. This means that the LIN synch break
SBRKTS
LIN Sync Field
Measurement
LDIV_MEAS
LIN Sync Field
Measurement
LDIV_MEAS
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