Table 45. Pwmx Output Level And Polarity - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto
PWM control register (PWMCR)
Read/write
Reset value: 0000 0000 (00h)
7
OE3
Bit 7:4 = OE[3:0] PWM Output Enable
These bits are set and cleared by software. They enable or disable the PWM output
channels independently acting on the corresponding I/O pin.
0: PWM output disabled.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They independently select the polarity of the
four PWM output signals.
Table 45.
Note: When an OPx bit is modified, the PWMx output signal polarity is immediately
reversed.
Duty cycle registers (PWMDCRx)
Read/write
Reset value: 0000 0000 (00h)
7
DC7
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
A PWMDCRx register is associated with the OCRx register of each PWM channel to
determine the second edge location of the PWM signal (the first edge location is common to
all channels and given by the ARTARR register). These PWMDCR registers allow the duty
cycle to be set independently for each PWM channel.
Input Capture control / status register (ARTICCSR)
Read/Write
Reset value: 0000 0000 (00h)
OE2 OE1
PWMx output level and polarity
PWMx output level
Counter <= OCRx
1
0
DC6 DC5
Doc ID 12468 Rev 3
OE0 OP3
Counter > OCRx
0
1
DC4 DC3
PWM auto-reload timer (ART)
OP2 OP1
DC2 DC1
0
OP0
OPx
0
1
0
DC0
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