Interrupt Register Description; Cpu Cc Register Interrupt Bits; Table 13. Interrupt Software Priority Levels; Figure 20. Nested Interrupt Management - STMicroelectronics ST72361 Auto Series Manual

Interrupts

Figure 20. Nested interrupt management

6.5

Interrupt register description

6.5.1

CPU CC register interrupt bits

Read/Write
Reset value: 111x 1010 (xAh)
7
1
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt software priority.
Table 13.
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable
1. TLI, TRAP and RESET events can interrupt a level 3 program.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see
52/279
IT1
IT2
RIM
IT4
MAIN
11 / 10
1 I1
Interrupt software priority levels
Interrupt software priority
(1)
)
Table 15: Dedicated interrupt instruction set on page
Doc ID 12468 Rev 3
TLI
IT0
IT1
IT3
IT4
H I0
Level
Low
High
ST72361xx-Auto
SOFTWARE
I1
PRIORITY
LEVEL
3 1 1
3 1 1
2 0 0
1 0 1
IT2
3 1 1
3 1 1
3/0
MAIN
10
N Z
I1
1
0
1
I0
0
C
I0
0
1
0
1
55).