Independent Pwm Signal Generation; Figure 40. Output Compare Control; Figure 41. Pwm Auto-Reload Timer Function - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto

Figure 40. Output compare control

11.2.5

Independent PWM signal generation

This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx
output pins with minimum core processing overhead. This function is stopped during HALT
mode.
Each PWMx output signal can be selected independently using the corresponding OEx bit
in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is
configured as output push-pull alternate function.
The PWM signals all have the same frequency which is controlled by the counter period and
the ARTARR register value.
f = f
PWM COUNTER
When a counter overflow occurs, the PWMx pin level is changed depending on the
corresponding OPx (output polarity) bit in the PWMCR register. When the counter reaches
the value contained in one of the output compare register (OCRx) the corresponding PWMx
pin level is restored.
It should be noted that the reload values will also affect the value and the resolution of the
duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the
OCRx register must be greater than the contents of the ARTARR register.
The maximum available resolution for the PWMx duty cycle is:
Resolution = 1 / (256 - ARTARR)
Note: To have the maximum resolution (1/256), the ARTARR register must be 0. With this
maximum resolution, 0% and 100% can be obtained by changing the polarity.

Figure 41. PWM auto-reload timer function

f
COUNTER
COUNTER FDh FEh
OCRx
PWMDCRx
PWMx
/ (256 - ARTARR)
255
DUTY CYCLE
REGISTER
(PWMDCRx)
AUTO-RELOAD
REGISTER
(ARTARR)
000
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
Doc ID 12468 Rev 3
ARTARR=FDh
FFh FDh FEh
FDh
FDh
PWM auto-reload timer (ART)
FFh FDh FEh
FEh
FEh
FFh
t
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