Dmm Lisa Map Registers: Dmm_Lisa_Map_0-Dmm_Lisa_Map_3; Dmm_Lisa_Map Registers; Dmm_Lisa_Map Registers Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

www.ti.com

2.4.4 DMM LISA MAP Registers: DMM_LISA_MAP_0-DMM_LISA_MAP_3

The DMM LISA MAP register is shown and described in the figure and table below.
31
Reserved
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-24 SYS_ADDR
23 Reserved
22-20 SYS_SIZE
19-18 SDRC_INTL
17-16 SDRC_ADDRSPC
15-10 Reserved
9-8 SDRC_MAP
7-0 SDRC_ADDR
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
Figure 2-60. DMM_LISA_MAP Registers
24
R-0
10 9
SDRC_MAP
R/W-0
Table 2-14. DMM_LISA_MAP Registers Field Descriptions
Value Description
0 DMM system section address MSB
0 Reserved
DMM system section size
0h 16-MB section
1h 32-MB section
2h 64-MB section
3h 128-MB section
4h 256-MB section
5h 512-MB section
6h 1-GB section
7h 2-GB section
SDRAM controller interleaving mode
0h No interleaving
1h 128-byte interleaving
2h 256-byte interleaving
3h 512-byte interleaving
0h Reserved. Should be 0.
0 Reserved
SDRAM controller mapping
0h Un-mapped
1h Mapped on SDRC 0 only (not interleaved)
2h Mapped on SDRC 1 only (not interleaved)
3h Mapped on SDRC 0 and SDRC 1 (interleaved)
0h SDRAM controller address MSB
© 2011, Texas Instruments Incorporated
23 22 20
Rsvd SYS_SIZE
R-0 R/W-0
8 7
Registers
19 18 17 16
SDRC_INTL SDRC_ADDRSPC
R/W-0 R/W-0
SDRC_ADDR
R/W-0
Type
R/W
R
R/W
R/W
R/W
R
R/W
R/W
DMM/TILER
0
387