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(5) Sequence of returning from stop mode
Sequence of returning from stop mode is oscillation start-up time and interrupt sequence.
When interrupt is generated in stop mode, CM10 becomes "0" and clearing stop mode.
Starting oscillation and supplying BCLK execute the interrupt sequence as follow:
In the interrupt sequence, the processor carries out the following in sequence given:
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Figure 2.16.2 shows the sequence of returning from stop mode.
BCLK
Address bus
Data bus
RD
WR
INTi
Note:
Shown above is the case where the main clock is selected for BCLK. If the sub-clock is selected for BCLK,
the sub-clock functions as BCLK when restored from stop mode, with the main clock's divide ratio
unchanged.
Figure 2.16.2. Sequence of returning from stop mode
(6) Registers related to power control
Figure 2.16.3 shows the memory map of power control-related registers, and Figure 2.16.4 shows
power control-related registers.
Figure 2.16.3. Memory map of power control-related registers
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
(a) CPU gets the interrupt information (the interrupt number and interrupt request level) by read-
ing address 00000
. The interrupt request bit of the interrupt written in address 00000
16
then be set to "0".
(b) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence in the temporary register (Note) within the CPU.
(c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer assignment
flag (U flag) to "0" (the U flag, however does not change if the INT instruction, in software
interrupt numbers 32 through 63, is executed)
(d) Saves the content of the temporary register (Note) within the CPU in the stack area.
(e) Saves the content of the program counter (PC) in the stack area.
(f) Sets the interrupt priority level of the accepted instruction in the IPL.
Note: This register cannot be utilized by the user.
After the interrupt sequence is completed, the processor resumes executing instruc-
tions from the first address of the interrupt routine.
Writing "1" to CM10
(all clock stop control bit)
Stop mode
Oscillation start-up
0006
System clock control register 0 (CM0)
16
0007
System clock control register 1 (CM1)
16
page 278 of 354
Operated by divided-by-8 mode
Address
Indeterminate
00000
Interrupt
Indeterminate
information
Indeterminate
Interrupt sequence approximately 20 cycle (13µ sec)
(Single-chip mode, f(X
) = 16MHz)
IN
2. Power Control
SP-2
SP-4
vec
vec+2
SP-2
SP-4
vec
vec+2
contents
contents
contents
contents
will
16
PC
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