Renesas M16C Series User Manual page 87

16-bit single-chip microcomputer
Hide thumbs Also See for M16C Series:
Table of Contents

Advertisement

M30245 Group
Example of wiring
www.DataSheet4U.com
Example of operation (when inversed format)
T r a n s f e r c l o c k
Receive enable
bit
(RE)
R
D
(Note)
X
i
T
D
( N o t e )
X
i
Signal line level
(Note)
R e c e i v e
c o m p l e t e f l a g
R e c e i v e i n t e r r u p t
r e q u e s t b i t
( I R )
Figure 2.4.16. Operation timing of reception in UART mode (used for SIM interface)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Microcomputer
TxD
i
RxD
i
CLK
i
Note1: TxDi pin is N-channel open drain and needs a pull-up resistance.
Note2: i=0 to 3
( 1 ) R e c e p t i o n e n a b l e d
( 2 ) S t a r t r e c e p t i o n
T c
"1"
"0"
S t a r t
b i t
S T
D
D
D
D
0
1
2
S T
D
D
D
D
0
2
1
"1"
( R I )
"0"
"1"
"0"
Shown in ( ) are bit symbols.
T h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s :
• P a r i t y i s e n a b l e d .
• O n e s t o p b i t .
• T r a n s m i t i n t e r r u p t c a u s e s e l e c t b i t = " 1 " .
N o t e : T x D
a n d R x D
a r e c o n n e c t e d i n t h e m a n n e r o f w i r e d O R a s s h o w n i n t h e c o n n e c t i o n d i a g r a m . S o T x D
i
i
b e c o m e t h e s a m e s i g n a l f r o m t h e l o g i c a l s t a n d p o i n t , b u t t h e o u t p u t s i g n a l s t u r n c o m p l e x , s o t h e y a r e s h o w n s e p a r a t e l y . A l s o ,
t h e s i g n a l l e v e l r e s u l t i n g f r o m c o n n e c t i n g T x D
page 78 of 354
(Note)
SIM card
External clock
(3) Receiving is completed
( 4 ) D a t a i s r e a d
Parity
S t o p
bit
b i t
D
D
D
D
P
SP
S T
7
3
4
5
6
D
S T
D
D
D
P
SP
3
7
4
5
6
R e a d t o r e c e i v e b u f f e r
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
fi : frequency of BRGi count source (f
f
frequency of BRGi count source (external clock)
EXT :
n : value set to BRGi
a n d R x D
i s s h o w n a s a s i g n a l l i n e l e v e l .
i
i
( 5 ) P a r i t y e r r o r o c c u r r e d
D
D
D
D
D
D
D
D
P
7
0
1
2
3
4
5
6
S i n c e a p a r i t y e r r o r o c c u r r e d , t h e
" L " l e v e l r e t u r n s f r o m T x D
i
D
D
D
D
D
D
D
D
P
0
2
3
7
1
4
5
6
Read to receive buffer
EXT
, f
, f
)
1
8
32
a n d R x D
i
2. SIM interface
S P
S P
o u g h t t o
i

Advertisement

Table of Contents
loading

Table of Contents