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M30245 Group
(3) Frequency division ratio
In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the
frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency division
ratio when a down count is performed, or [FFFF
ratio when an up count is performed. In one-shot timer mode, the value set in the timer register be-
comes the frequency division ratio.
The counter overflows (or underflows) when a count source equal to a frequency division ratio is input,
and an interrupt occurs. For the pulse output function, the output from the port varies (the value in the
port register does not vary).
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(4) Reading the timer
Either in timer mode or in event counter mode, reading the timer register takes out the count at that
moment. Read it in 16-bit units. The data either in one-shot timer mode or in pulse width modulation
mode is indeterminate.
(5) Writing to the timer
To write to the timer register when a count is in progress, the value is written only to the reload register.
When writing to the timer register when a count is stopped, the value is written both to the reload
register and to the counter. Write a value in 16-bit units.
(6) Relation between the input/output to/from the timer and the direction register
With the output function of the timer, pulses are output regardless of the contents of the port direction
register. To input an external signal to the timer, set the port direction register to input.
(7) Pins related to timer A
(a) TA0
(b) TA0
(8) Registers related to timer A
Figure 2.2.1 shows the memory map of timer A-related registers. Figures 2.2.2 through 2.2.5 show
timer A-related registers.
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
, TA1
, TA2
, TA3
, TA4
IN
IN
IN
IN
, TA1
, TA2
, TA3
OUT
OUT
OUT
OUT
page 7 of 354
- the set value + 1] becomes the frequency division
16
Input pins to timer A.
IN
, TA4
Output pins from timer A. They become input pins to
OUT
timer A when event counter mode is active.
2. Timer A
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