Renesas M16C Series User Manual page 251

M30245 Group
DMA0 request cause select register (Note 1)
b7 b6
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DMA1 request cause select register (Note 1)
b7 b6
Figure 2.10.2. DMAC-related registers (1)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
b5 b4 b3 b2 b1 b0
Symbol
DM0SL
Bit Symbol
DSEL0
DSEL1
DSEL2
DSEL3
DSEL4
Nothing is assigned. Write "0" when writing to these bits. The value is "0" when read.
DSR
Note 1: Software is always enabled.
Note 2: SSI=Serial sound interface
Note 3: This value should not be set.
b5 b4 b3 b2 b1 b0
Symbol
DM1SL
Bit Symbol
DSEL0
DSEL1
DSEL2
DSEL3
DSEL4
Nothing is assigned. Write "0" when writing to these bits. The value is "0" when read.
DSR
Note 1: Software is always enabled.
Note 2: SSI=Serial sound interface
Note 3: This value should not be set.
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Address
03B8
16
Bit Name
b4 b3 b2 b1 b0
0 0 0 0 0 : DMA Disabled
DMA request
0 0 0 0 1 : INT0 (falling edge)
0 0 0 1 0 : INT0 (two edges)
cause select bits
0 0 0 1 1 : USB0
0 0 1 0 0 : Timer A0
0 0 1 0 1 : Timer A1
0 0 1 1 0 : Timer A2
0 0 1 1 1 : Timer A3
0 1 0 0 0 : Timer A4
0 1 0 0 1 : UART0 receive/ACK/SSI0 receive
0 1 0 1 0 : UART1 receive/ACK/SSI1 receive
0 1 0 1 1 : UART2 receive/ACK
0 1 1 0 0 : UART3 receive/ACK
0 1 1 0 1 : UART0 transmit/NACK/SSI0 transmit
0 1 1 1 0 : UART1 transmit/NACK/SSI1 transmit
0 1 1 1 1 : UART2 transmit/NACK
1 0 0 0 0 : UART3 transmit/NACK
1 0 0 0 1 : A/D
1 0 0 1 0 : Disabled (Note 3)
1 0 0 1 1 : DMA1
1 0 1 0 0 : DMA2
1 0 1 0 1 : DMA3
1 0 1 1 0 : Disabled (Note 3)
1 0 1 1 1 : Disabled (Note 3)
1 1 x x x : Disabled (Note 3)
Software trigger is always enabled
Software DMA
request bit Write "1" to trigger DSR bit.
Address
03BA
16
Bit Name
b4 b3 b2 b1 b0
0 0 0 0 0 : DMA Disabled
DMA request 0 0 0 0 1 : INT1 (falling edge)
0 0 0 1 0 : INT1 (two edges)
cause select bits
0 0 0 1 1 : USB1
0 0 1 0 0 : Timer A0
0 0 1 0 1 : Timer A1
0 0 1 1 0 : Timer A2
0 0 1 1 1 : Timer A3
0 1 0 0 0 : Timer A4
0 1 0 0 1 : UART0 receive/ACK/SSI0 receive
0 1 0 1 0 : UART1 receive/ACK/SSI1 receive
0 1 0 1 1 : UART2 receive/ACK
0 1 1 0 0 : UART3 receive/ACK
0 1 1 0 1 : UART0 transmit/NACK/SSI0 transmit
0 1 1 1 0 : UART1 transmit/NACK/SSI1 transmit
0 1 1 1 1 : UART2 transmit/NACK
1 0 0 0 0 : UART3 transmit/NACK
1 0 0 0 1 : A/D
1 0 0 1 0 : DMA0
1 0 0 1 1 : Disabled (Note 3)
1 0 1 0 0 : DMA2
1 0 1 0 1 : DMA3
1 0 1 1 0 : Disabled (Note 3)
1 0 1 1 1 : Disabled (Note 3)
1 1 x x x : Disabled (Note 3)
Software trigger is always enabled
Software DMA
request bit Write "1" to trigger DSR bit.
When reset
00
16
Function (Note 2) R W
O O
O O
O O
O O
O O
_ _
O O
When reset
00
16
Function (Note 2) R W
O O
O O
O O
O O
O O
_ _
O O
2. DMAC