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Table 2.9.9. Variation of the successive comparison register and Vref while A/D conversion is in
A/D converter stopped
1st comparison
2nd comparison
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3rd comparison
10th comparison
Conversion complete
Result of A/D conversion
3FF
16
3FE
16
003
16
002
16
001
16
000
16
Figure 2.9.18. Theoretical A/D conversion characteristics (10-bit mode)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
progress (10-bit mode)
Successive approximation register
b9
1
0 0 0 0 0 0 0 0 0
1
0 0 0 0 0 0 0 0 0
n
1 0 0 0 0 0 0 0 0
9
1st comparison result
n
n
1 0 0 0 0 0 0 0
9
8
2nd comparison result
n
n
n
n
n
n
9
8
7
6
5
4
n
n
n
n
n
n
9
8
7
6
5
4
This data transfers to the bit 0
to bit 9 of AD register i.
Theoretical A/D
conversion characteristic
V
V
REF
REF
0
x 1
1024
1024
V
REF
x 0.5
1024
page 232 of 354
b0
V
REF
[V]
2
V
V
REF
REF
–
2
2048
V
V
REF
REF
2
4
±
V
V
REF
REF
±
2
4
V
V
REF
REF
n
n
n
1
3
2
1
±
2
4
n
n
n
n
3
2
1
0
V
V
REF
REF
x 2
x 3
x 1021
1024
1024
V
change
ref
[V]
V
REF
n
= 1
+
9
V
4
REF
[V]
–
V
REF
2048
n
= 0
–
9
4
n
= 1
8
V
V
REF
REF
±
–
[V]
n
= 0
8
2048
8
V
V
V
REF
REF
REF
± ...... ±
–
±
8
1024
2048
Ideal A/D conversion
characteristic
V
x 1022 V
REF
REF
x 1023
1024
1024
Analog input voltage
2. A/D Converter
V
REF
+
8
V
REF
–
8
[V]
V
REF
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