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M30245 Group
Example of wiring
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Example of operation
Transfer clock
Port
Transmit
enable bit (TE)
Transmit
buffer empty
flag (Tl)
CLKi
TxDi
Transmit register
empty flag
(TXEPT)
Transmit
interrupt request
bit (IR)
Figure 2.5.8. Operation timing of transmission in serial interface special function master mode, without clock delay
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Microcomputer
Port
SSi
CLKi
T
Di
X
(1) Output "L" at the receiver side IC
(2) Transmission enabled
(3) Start transmission Tc
"H"
"L"
"1"
"0"
Data is set to UARTi transmit buffer register
"1"
"0"
Transferred from UARTi transmit buffer register to UARTi transmit register
T
CLK
D
D
D
D
D
0
3
1
2
"1"
"0"
"1"
"0"
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CLK polarity select bit = "0".
• Transmit interrupt cause select bit = "0".
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(4) Transmission is complete
(5) Transmit next data
D
D
D
D
D
D
D
D
7
0
1
2
3
4
4
5
6
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc = T
= 2(n + 1) / fi
CLK
fi: frequency of BRGi count source (f
n: value set to BRGi
2. Serial Interface Special Function
Receiver side IC
SS
CLK
SR
D
X
D
D
D
D
D
D
D
D
D
5
6
7
0
1
2
3
4
5
, f
, f
)
1
8
32
D
D
6
7
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