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M30245 Group
Frequency Multiplier
f
VCO
Frequency Multiply register is set to 255, multiplication is disabled and f
should be set so that f
synthesizer multiply register is set.
f
VCO
Table 2.7.2. Example of Setting the Frequency Multiply Register (FSM)
f
PIN
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1 MH
2 MH
4 MH
6 MH
8 MH
12 MH
Frequency Divider
Clock f
register (FSD). When the frequency synthesizer divider register is set to 255, division is disabled and
f
SYN
set.
f
SYN
Note 1: Set f
Table 2.7.3. Example of Setting the frequency synthesizer divide register (FSD)
f
VCO
48 MH
Note 1: f
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
is generated via the Frequency Synthesizer Mul-tiply register (FSM: address 03DD
becomes 48MHz. Table 2.7.2 shows some examples of how the frequency
VCO
= f
X 2(n+1) n: FSM value
PIN
FSM Value
Dec (Hex)
23 (17
Z
16
11 (0B
Z
16
5 (05
Z
16
3 (03
Z
16
2 (02
Z
16
1 (01
Z
16
is a divided down version of f
SYN
= f
. Table 2.7.3 shows some examples of how the frequency synthesizer division register is
VCO
= f
/ 2(m+1) m: FSD value
VCO
to 12MHz or lower.
SYN
FSD Value
Dec (Hex)
1 (01
16
2 (02
16
2 (02
Z
16
3 (03
16
127 (7F
=f
/(m+1) when FSCCR4=1 and m=2.
SYN
VCO
page 125 of 354
f
VCO
48 MH
)
Z
48 MH
)
Z
48 MH
)
Z
48 MH
)
Z
48 MH
)
Z
48 MH
)
Z
. f
is generated via the frequency synthesizer divide
VCO
SYN
f
SYN
12.00 MH
)
8.00 MH
)
16.00 MH
)
Z
6.00 MH
)
187.50 kH
)
16
2. Frequency synthesizer (PLL)
= f
VCO
PIN
Z
Z
(Note 1)
Z
Z
). When the
16
. The value of n
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