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M30245 Group
• SET_DATA_END bit
This bit controls setting of the DATA_END flag to "1".
When the last data has been written in IN FIFO in the IN data phase or when the last data has been
read from OUT FIFO in the OUT data phase, set this bit to "1". When this bit is set to "1", the
DATA_END flag is set to "1". At this time simultaneously, set the CLR_OUT_BUF_RDY bit or
SET_IN_BUF_RDY bit to "1".
Completion of processing of the data which had amount of data set by setup phase is notified to the
USB function control unit, and the process shifts into status phase processing.
• CLR_FORCE_STALL bit
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This bit controls clearing of the FORCE_STALL flag.
When this bit is written to "1", the FORCE_STALL flag is cleared to "0".
• SEND_STALL bit
This bit controls the STALL response to the host CPU.
To responds with STALL when an invalid request has received from the host CPU, set this bit to "1"
simultaneously as CLR_OUT_BUF_RDY bit is set to "1".
When this bit is set to "1", the USB function control unit transmits, to the host CPU, the STALL
handshake concerning all the IN/OUT transactions. When a new valid SETUP packet is received,
clear a data by writing "0" in this bit.
• DATA_END_MASK bit
This bit controls whether the DATA_END flag clear becomes an endpoint 0 interrupt factor.
When this bit is set to "1", clearing the DATA_END flag does not become an endpoint 0 interrupt
factor. This bit is set to "1" at the time of reset.
The configuration of USB endpoint 0 control and status register is shown in Figure 2.8.32.
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
page 172 of 354
2. USB function
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