Renesas M16C Series User Manual page 329

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Figure 3.7.4. Setting routine (3) of DMA transfer from USB OUT FIFO to serial sound interface
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Continued from the previous page
The DMA request of the serial sound interface 1 transmit is occurred
when DMA enable bit = "1" and the OUT_BUF_STS1 flag of endpoint 1 = "1".
DMA request from the 2nd byte on is occurred
when DMA enable bit = "1" and the OUT_BUF_STS1 flag of endpoint 1 = "1".
DMA0 transfer from the 2nd word on
Completion of the DMA0 transfer and occurrence of the DMA0 interrupt request.
Setting CLR_OUT_BUF_RDY bit of endpoint 1 to "1" and completion of one receive
packet data fetch after confirming of the DMA0 interrupt request.
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To subsequently start DMA0 transfer:
Disable DMA0 once and set the DMA0 related registers again.
page 320 of 354
DMA0 transfer of the 1st word
DMA enable bit is set to "0"
by underflow of the DMA0 transfer counter.
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USB Endpoint 1 OUT Control and Status register
EP1OCS [Address 02B6
CLR_OUT_BUF_RDY bit
1 : Data set unloaded from the OUT FIFO
(updates OUT_BUF_STS1 and OUT_BUF_STS0)
3. USB Applications
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