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M30245 Group
Transmission
Reception
www.DataSheet4U.com
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
(1) With an external clock selected, perform the following set-up procedure with the CLKi pin
input level = "H" if the CLK polarity select bit = "0" or with the CLKi pin input level = "L" if the
CLK polarity select bit = "1":
1. Set the transmit enable bit (to "1")
2. Write transmission data to the UARTi transmit buffer register
3. "L" level input to the CTSi pin (when the CTS function is selected)
(1) In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock.
Fix settings for transmission even when using the device only for reception. Dummy data is
output to the outside from the TxDi pin (transmission pin) when receiving data.
(2) With the internal clock selected, setting the transmit enable bit to "1" (transmission-enabled
status) and setting dummy data in the UARTi transmission buffer register generates a shift
clock.
With the external clock selected, a shift clock is generated when the transmit enable bit is set
to "1", dummy data is set in the UARTi transmit buffer register, and the external clock is input
to the CLKi pin.
(3) When receiving data in succession, an overrun error occurs if the serial interface starts re-
ceiving the next data item while the receive complete flag is 1 (before reading the contents of
the UARTi receive buffer register) and receives the 7th bit of the next data item, and then the
overrun error flag is set to "1". In this instance, the next data is written to the UARTi receive
buffer register, so handle with this problem by writing programs on transmission side and
reception side so that the previous data is transmitted again.
If an overrun error occurs, the UARTi receive interrupt request bit does not go to "1".
(4) To receive data in succession, set dummy data in the lower-order byte of the UARTi transmit
buffer register every time reception is made. In continuous receive mode, when the receive
buffer is read out,the unit simultaneously goes to a receive enable state without having to set
dummy data back to the transmit buffer register again.
(5) With an external clock selected, perform the following set-up procedure with the CLKi pin
input level = "H" if the CLK polarity select bit = "0" or with the CLKi pin input level = "L" if the
CLK polarity select bit = "1":
1. Set receive enable bit (to "1")
2. Set transmit enable bit (to "1")
3. Write dummy data to the UARTi transmit buffer register
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(6) Output from the RTS pin goes to "L" level as soon as the receive enable bit is set to "1". This
is not related to the content of the transmit buffer empty flag or the content of the transmit
enable bit. Output from the RTS pin goes to "H" level when reception starts, and goes to "L"
level when reception is completed. This is not related to the content of the transmit buffer
empty flag or the content of the receive complete flag.
page 54 of 354
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2. Clock-Synchronous Serial I/O
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