Renesas M16C Series User Manual page 175

M30245 Group
(4) USB Suspend Interrupt Request Processing Routine
When using the USB suspend interrupt, set USB suspend interrupt control register (address 0056
In the USB suspend interrupt, when the USB suspend status flag (SUSPEND) of USB power manage-
ment register is set to "1", the interrupt request occurs.
The USB suspend interrupt request processing routine is shown in Figure 2.8.28 and Figure 2.8.29.
Setting USB control register
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b7
Clearing the protect
b7
Setting frequency synthesizer control register
b7
Setting the interruppt for return from suspend mode (Note1, 2)
b7
Note 1: Confirms that the interrupt enable flag (I) of flag register is set to "0" before setting the interrupt to
Note 2: When the interrupt is not used to clear the stop mode, the interrupt should be disabled by setting
Figure 2.8.28. USB suspend interrupt request processing routine (1)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Detection of USB suspend interrupt request
b0
USB control register [Address 000C
0 0 0 0 0 0
USBC
USB clock enable bit
0: Disable (48MHZ clock supply disabled
b0
Protect register [Address 000A
1
0
PRCR
Enable bit for writing to system clock control registers 0 and 1
and frequency synthesizer related registers
1 : Write-enabled
b0
Frequency synthesizer control register [Address 03DC
0
0 0
FSC
Frequency Synthesizer enable bit
0 : Disabled
b0
USB resume interrupt control register [Address 0058
0
RSMIC
Interrupt priority level select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt request bit
0 : Interrupt not requested
higher priority level than the USB suspend interrupt. The interrupt should be higher priority level than
the USB suspend interrupt when those event are returned from the suspend mode by process
(key input interrupt, etc.) other than the USB resume interrupt.
the interrupt priority level to "0".
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2. USB function
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