Renesas M16C Series User Manual page 108

M30245 Group
Example of wiring
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Example of operation
Transfer clock
Port
Receive enable
bit (RE)
Transmit
enable bit (TE)
Transmit buffer
empty flag (Tl)
Receive complete
flag (Rl)
Receive interrupt
request bit (IR)
Figure 2.5.11. Operation timing of reception in serial interface special function master mode, with clock delay
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Microcomputer
Port
SSi
CLKi
R
X
(1) Output "L" on the transmitter side IC
(2) Reception enabled
(3) Start reception
"H"
"L"
"1"
"0"
"1"
"0"
Dummy data is set in UARTi transmit buffer register
"1"
"0"
TCLK
CLKi
RxDi
D D D
0 1
Transferred from UARTi receive register
to UARTi receive buffer register
"1"
"0"
"1"
"0"
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CLK polarity select bit = "0".
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Di
(4) Reception is complete
(5) Read of reception data
Tc
Transferred from UARTi transmit buffer register to UARTi transmit register
Reception data is taken in
D D D D D D D D
2 3 4 5 6 7 0 1 2
Read out from UARTi receive buffer register
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc = T
CLK
fi: frequency of BRGi count source (f
n: value set to BRGi
2. Serial Interface Special Function
Transmitter side IC
SS
CLK
ST D
X
D D D D D D D D D
3 4 5 6 7 0 1 2
= 2(n + 1) / fi
, f , f
1 8
D D D D
3 4 5 6 7
)
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