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M30245 Group
(6) Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the
highest priority level. Figure 2.15.5 shows the circuit that judges the interrupt priority level.
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Figure 2.15.5. Interrupts resolution circuit
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Priority level of each interrupt
Level 0 (initial value)
INT2
Vbus detection
USB reset
USB resume
USB
suspend
USB EP0
INT1
INT0
USB function
USB SOF
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
DMA3
DMA2
DMA1
DMA0
UART0 reception/ACK
/SSI0 reception
UART1 reception/ACK
/SSI1 reception
UART2 reception/ACK
UART3 reception/ACK
UART0 transmission/NACK
/SSI0 transmission
UART1 transmission/NACK
/SSI1 transmission
UART2 transmission/NACK
UART3 transmission/NACK
A/D conversion
UART0/UART2 Bus collision detection,
Start/stop condition detection
UART1/UART3 Bus collision detection,
Start/stop condition detection
Key input interrupt
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
Address match
Watchdog timer
DBC
NMI
Reset
page 271 of 354
High
Priority of peripheral I/O interrupts
(if priority levels are same)
DMA0
Low
2. Multiple Interrupts
Interrupt
request
accepted
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