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DMAi control register
b7
b6
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DMAi source pointer (i=0-3)
(b23)
b7
DMAi destination pointer (i=0-3)
(b23)
b7
DMAi transfer counter (i=0-3)
(b15)
b7
Figure 2.10.4. DMAC-related registers (3)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
b5
b4
b3
b2
b1
b0
DMiCON (i=0-3)
Bit Symbol
DMBIT
DMASL
DMAS
DMAE
DSD
DAD
Nothing is assigned. Write "0" when writing to these bits. The value is "0" when read.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to "0".
Note 3: Source address direction select bit and destination address direction select bit cannot
be set to "1" simultaneously.
(b19)
(b16)(b15)
b3
b0
b7
(b19)
(b16)(b15)
b3
b0
b7
(b8)
b0
b7
page 244 of 354
Address
Symbol
002C
, 003C
16
018C
, 019C
16
Bit Name
Transfer unit select bit
Repeat transfer mode select bit
DMA request bit (Note 1)
DMA enable bit
Source address
direction select bit (Note 3)
Destination address
direction select bit (Note 3)
(b8)
b0
b7
Function
Source pointer
stores the source address
Nothing is assigned.
Write "0" when writing to these bits. The value is "0" when read.
(b8)
b0
b7
Function
Destination pointer
stores the destination address
Nothing is assigned.
Write "0" when writing to these bits. The value is "0" when read.
Symbol
Address
TCR0
0029
b0
TCR1
0039
TCR2
0189
TCR3
0198
Function
Transfer counter
Set a value one less than the transfer count
When reset
,
16
00000X00
16
Function
0 : 16 bits
1 : 8 bits
0 : Single transfer
1 : Repeat transfer
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
0 : Fixed
1 : Forward
Symbol
Address
SAR0
0022
o 0020
16 t
16
b0
SAR1
0032
o 0030
16 t
16
SAR2
0182
o 0180
16 t
16
SAR3
0192
o 0190
16 t
16
Transfer address
specification
00000
to FFFFF
16
Symbol
Address
DAR0
0026
o 0024
16 t
16
b0
DAR1
0036
o 0034
16 t
16
DAR2
0186
o 0184
16 t
16
DAR3
0196
o 0194
16 t
16
Transfer address
specification
00000
to FFFFF
16
When reset
o 0028
Indeterminate
16 t
16
o 0038
Indeterminate
16 t
16
o 0188
Indeterminate
16 t
16
o 0198
Indeterminate
16 t
16
Transfer count
specification
00000
to FFFFF
16
2. DMAC
2
R W
O O
O O
O O
(Note 2)
O O
O O
O O
_ _
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
R W
O O
16
_ _
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
R W
O O
16
_ _
R W
O O
16
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