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(3) DMA Request by Endpoint x IN
DMA Request Factor
When endpoint x(x=1 to 4) IN FIFO write request select bit is set to the DMA request factor origin of
USB0/USB1/USB2/USB3, the DMA request factor includes the following three kinds. On occurrence
of an event when all the specified conditions have been satisfied for each factor, the DMA request of
DMA0/DMA1/DMA2/DMA3 occurs.
•Factor 1
Conditions:
- DMA enable bit of DMAi control register is set to "1" (enable).
- Any oneendpoint x(x=1 to 4) IN FIFO write request select bit in USB DMAx(x=0 to 3) request
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Event:
•Factor 2
Conditions:
- DMA enable bit of DMAi control register is set to "1" (enable).
- The IN_BUF_STS1 and IN_BUF_STS0 flags of endpoint x IN which is set in USB DMAx(x=0 to
- There is no selection of USB DMAx(x=0 to 3) request register ("00
Event:
•Factor 3
Conditions:
- DMA enable bit of DMAi control register is set to "1" (enable).
- The IN_BUF_STS1 and IN_BUF_STS0 flags of endpoint x IN which is set in USB DMAx(x=0 to
- Any one of endpoint x(x=1 to 4) IN FIFO write request select bit in USB DMAx(x=0 to 3) request
Event:
DMA Transfer to Endpoint x IN FIFO
The DMA request factor of USB0/USB1/USB2/USB3 corresponds to write in the endpoints 1~4 IN
FIFO (Factor 3). Therefore, with endpoint x IN FIFO being specified to the DMA destination pointer
and the transfer destination address direction being fixed, when DMA transfer is executed by Factor
1 (Factor 2 or Factor 3), Factor 3 occurs. Therefore, when one buffer data is written in IN FIFO by
DMA transfer, it is possible that the 1st byte (1st word) data is DMA transferred by Factor 1 (Factor 2
or Factor 3) and the other data, starting from the 2nd byte (2nd word) up to the last byte (last word),
are DMA transferred by Factor 3.
For details of DMA transfer, refer to "Chapter 2.10 DMAC".
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
register is set to "1". The other bits are set to "0" (valid setting).
The IN FIFO state of the endpoint x IN which is set in USB DMAx(x=0 to 3) request register has
been updated, and the IN_BUF_STS1 and IN_BUF_STS0 flags are set to "00
single buffer and "01
" at the time of double buffer. (When there are the space of one or more
2
packets in the IN FIFO. At this time, when one packet transfer is completed, the endpoint x IN
interrupt request simultaneously occurs.)
3) request register are set to "00
the IN FIFO.)
Any one endpoint x(x=1 to 4) IN FIFO write request select bit in USB DMAx(x=0 to 3) request
register is set to "1". The other bits are set to "0" (valid setting).
3) request register are set to "00
the IN FIFO.)
register is set to "1". The other bits are set to "0" (valid setting).
1-byte (1-word) data is written in the endpoint x IN FIFO which is set in USB DMAx(x=0 to 3)
request register .
page 209 of 354
" or "01
". (When there are the space of one or more packets in
2
2
" or "01
". (When there are the space of one or more packets in
2
2
2. USB function
" at the time of
2
").
16
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