Renesas M16C Series User Manual page 217

M30245 Group
(2) DMA Request by Endpoint x OUT
DMA Request Factors
When endpoint 1 to 4 OUT FIFO write request select bit is set to the DMA request factor origin of
USB0/USB1/USB2/USB3, the DMA request factor includes the following three kinds. On occurrence
of an event when all the specified conditions have been satisfied for each factor, the DMA request of
DMA0/DMA1/DMA2/DMA3 occurs.
•Factor 1
Conditions:
- DMA enable bit of DMAi control register is set to "1" (enable).
- Any one of endpoint x(x=1 to 4) OUT FIFO read request select bit in USB DMAx(x=0 to 3)
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Event:
•Factor 2
Conditions:
- DMA enable bit of DMAi control register is set to "1" (enable).
- The OUT_BUF_STS1 and OUT_BUF_STS0 flags of endpoint x OUT which is set in USB
- There is no selection of USB DMAx(x=0 to 3) request register ("00
Event:
•Factor 3
Conditions:
- DMAenable bit of DMAi control register is set to "1" (enable).
- The OUT_BUF_STS1 and OUT_BUF_STS0 flags of endpoint x OUT which is set in USB
- Any one of endpoint x(x=1 to 4) OUT FIFO read request select bit in USB DMAx(x=0 to 3)
Event:
Reading of Endpoint x OUT FIFO in DMA Transfer
The DMA request factor of USB0/USB1/USB2/USB3 corresponds to read from the endpoints 1 to 4
OUT FIFO (Factor 3). Therefore, with endpoint x OUT FIFO being specified to the DMA source pointer
and the transfer source address direction being fixed, when DMA transfer is executed by Factor 1
(Factor 2 or Factor 3), Factor 3 occurs. Therefore, when one buffer data (one packet data) is read from
OUT FIFO by DMA transfer, it is possible that the 1st byte (1st word) data is DMA transferred by
Factor 1 (Factor 2 or Factor 3) and the other data, starting from the 2nd byte (2nd word) up to the last
byte (last word), are DMA transferred by Factor 3.
For details of DMA transfer, refer to "Chapter 2. DMAC".
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
request register is set to "1". The other bits are set to "0" (valid setting).
The OUT FIFO state of the endpoint x OUT which is set in USB DMAx(x=0 to 3) request register
has been updated, and the OUT_BUF_STS1 and OUT_BUF_STS0 flags are set to "11
time of single buffer and "10
received in OUT FIFO. At this time, when one packet receive is completed, the endpoint x OUT
interrupt request simultaneously occurs.)
DMAx(x=0 to 3) request register are set to "10
received in OUT FIFO.)
Any one of endpoint x(x=1 to 4) OUT FIFO read request select bit in USB DMAx(x=0 to 3)
request register is set to "1". The other bits are set to "0" (valid setting).
DMAx(x=0 to 3) request register are set to "10
received in OUT FIFO.)
request register is set to "1". The other bits are set to "0" (valid setting).
1-byte (1-word) data is read from the endpoint x OUT FIFO which is set in USB DMAx(x=0 to 3)
request register .
page 208 of 354
" at the time of double buffer. (When data of one or more buffers are
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2. USB function
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