Virtex-Ii Fpga Fabric - Xilinx ML310 User Manual

Virtex-II Pro
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Virtex-II FPGA Fabric

Description of the Virtex-II Family fabric follows:
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ML310 User Guide
UG068 (v1.01) August 25, 2004
Four levels of selectable pre-emphasis
Five levels of output differential voltage
Per-channel internal loopback modes
2.5V transceiver supply voltage
SelectRAM memory hierarchy
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Up to 10 Mb of True Dual-Port RAM in 18 Kb block SelectRAM resources
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Up to 1.7 Mb of distributed SelectRAM resources
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High-performance interfaces to external memory
Arithmetic functions
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Dedicated 18-bit x 18-bit multiplier blocks
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Fast look-ahead carry logic chains
Flexible logic resources
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Up to 111,232 internal registers/latches with Clock Enable
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Up to 111,232 look-up tables (LUTs) or cascadable variable (1 to 16 bits) shift
registers
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Wide multiplexers and wide-input function support
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Horizontal cascade chain and Sum-of-Products support
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Internal 3-state busing
High-performance clock management circuitry
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Up to eight Digital Clock Manager (DCM) modules
- Precise clock de-skew
- Flexible frequency synthesis
- High-resolution phase shifting
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16 global clock multiplexer buffers in all parts
Active Interconnect technology
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Fourth-generation segmented routing structure
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Fast, predictable routing delay, independent of fanout
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Deep sub-micron noise immunity benefits
Select I/O-Ultra technology
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Up to 852 user I/Os
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Twenty two single-ended standards and five differential standards
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Programmable LVTTL and LVCMOS sink/source current (2 mA to 24 mA) per
I/O
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Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for
single-ended I/O standards
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PCI support(1)
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Differential signaling
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