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TMS320C6455
SPRS276M – MAY 2005 – REVISED MARCH 2012
1.3
Functional Block Diagram
Figure 1-2
shows the functional block diagram of the C6455 device.
32
DDR2
DDR2 SDRAM
Mem Ctlr
PLL2 and
SBSRAM
PLL2
Controller
ZBT SRAM
64
EMIFA
SRAM
TCP2
ROM/FLASH
VCP2
I/O Devices
McBSP0
McBSP1
Serial
RapidIO
HPI (32/16)
PCI66
UTOPIA
EMAC
10/100/1000
RMII
GMII
RMGII
MDIO
16
GPIO16
I2C
Timer1
HI
LO
Timer1
LO
A. McBSPs: Framing Chips - H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs.
B. The PCI peripheral pins are muxed with some of the HPI peripheral pins and the UTOPIA address pins.
For more detailed information, see the
C. Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as a 64-bit general-purpose timer, dual 32-bit general-purpose timers,
or a watchdog timer.
D. The PLL2 controller also generates clocks for the EMAC.
E. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
4
Features
(D)
(A)
(A)
L2Cache
Memory
(B)
(B)
Primary
(B)
Switched
Central
Resource
MII
(D)
(B)
(C)
(C)
HI
Device Configuration
Figure 1-2. Functional Block Diagram
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Product Folder Link(s):
L1P SRAM/Cache Direct-Mapped
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
C64x+ DSP Core
Instruction Fetch
16-/32-bit
Instruction Dispatch
Instruction
Decode
M
e
2048K
Data Path A
g
Bytes
a
A Register File
m
A31−A16
o
A15−A0
d
u
l
e
.M1
.L1
.S1
xx
xx
L1D Memory Controller (Memory Protect/Bandwidth Mgmt)
L1D SRAM/Cache
2-Way Set-Associative
32K Bytes Total
EDMA 3.0
Secondary
Switched Central
Resource
section.
Copyright © 2005–2012, Texas Instruments Incorporated
TMS320C6455
32K Bytes
Control Registers
SPLOOP Buffer
In-Circuit Emulation
Data Path B
B Register File
B31−B16
B15−B0
.M2
.D1
.D2
xx
.S2
.L2
xx
Device
PLL1 and
Configuration
PLL1
Logic
Controller
Boot Configuration
www.ti.com
C6455
L2 ROM
32K
(E)
Bytes
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