Table of Contents
Advertisement
www.ti.com
1.3
C6474 Functional Block Diagram
Figure 1-2
shows the functional block diagram of the C6474 device.
32
DDR2 Memory
Controller
PLL2
2
Serial RapidIO
(2x)
TCP2
VCP2
McBSP0
McBSP1
EMAC
10/100/1000
SGMII
MDIO
I2C
16
GPIO16
FSYNC
Antenna
Interface
Timer [0-5]
Copyright © 2008–2010, Texas Instruments Incorporated
DSP Subsystem 2
DSP Subsystem 1
DSP Subsystem 0
C64x+ Megamodule
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
Instruction Fetch
16-/32-bit
Instruction Dispatch
Instruction Decode
A Register File
A31 - A16
A15 - A0
.M1
.L1
.S1
xx
xx
L1 Data Memory Controller (Memory Protect/Bandwidth Mgmt)
L1D SRAM/Cache 2-Way
EDMA 3.0
L3 ROM
Figure 1-2. Functional Block Diagram
Submit Documentation Feedback
Product Folder Link(s)
:TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
32K Bytes
L1P SRAM/Cache
Direct-Mapped
C64x+ DSP Core
Control Registers
SPLOOP Buffer
In-Circuit Emulation
B Register File
B31 - B16
B15 - B0
.M2
.D1
.D2
xx
.S2
.L2
xx
32K Bytes Total
Set Associative
Semaphore
PLL1 and
Power-Down and Device
PLL1 Controller
Configuration Logic
Boot Configuration
TMS320C6474
Features
5
Advertisement
Table of Contents
