S1D13704 Hardware Configuration - Epson S1D13704 Technical Manual

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4.3 S1D13704 Hardware Configuration

Signal
CNF0
CNF1
CNF2
CNF3
CNF4
CNF2
0
0
0
0
1
1
1
1
1
1
S1D13704
X26A-G-010-03
The S1D13704 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the S1D13704 Hardware
Functional Specification, document number X26A-A-001-xx for details.
The tables below show only those configuration settings important to the MPC821
interface. The settings are very similar to the ISA bus with the following exceptions:
• the WAIT# signal is active high rather than active low.
• the Power PC is big endian rather than little endian.
Table 4-2: Configuration Settings
Low
See "Host Bus Selection" table below See "Host Bus Selection" table below
Little Endian
Active low LCDPWR signal
= configuration for MPC821 host bus interface
Table 4-3: Host Bus Selection
CNF1 CNF0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 0
1 1
1 1
= configuration for MPC821 host bus interface
High
Big Endian
Active high LCDPWR signal
*
BS# Host Bus Interface
X SH-4 interface
X SH-3 interface
X reserved
X MC68K #1, 16-bit
X reserved
X MC68K #2, 16-bit
0 reserved
1 reserved
0 Generic #1, 16-bit
1 Generic #2, 16-bit
Interfacing to the Motorola MPC821 Microprocessor
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/12