Motorola M68K #2 Interface Timing; Table 7-4: M68K #2 Timing (Mc68030); Figure 7-4: M68K #2 Timing (Mc68030) - Epson S1D13704 Technical Manual

Epson Research and Development
Vancouver Design Center

7.1.4 Motorola M68K #2 Interface Timing

CLK
A[15:0]
CS#
SIZ0, SIZ1
R/W#
AS#
DS#
DSACK1#
D[31:16]
(write)
D[31:16]
(read)
Symbol
f Bus Clock frequency
CLK
T Bus Clock period
CLK
t1 A[15:0], CS#, SIZ0, SIZ1 valid before AS# falling edge
t2 A[15:0], CS#, SIZ0, SIZ1 hold from AS#, DS# rising edge
t3 AS# low to DSACK1# driven high
t4 CLK to DSACK1# low
t5 AS# high to DSACK1# high
t6 AS# high to DSACK1# high impedance
t7 DS# falling edge to D[31:16] valid (write cycle)
t8 AS#, DS# rising edge to D[31:16] invalid (write cycle)
t9 D[31:16] valid to DSACK1# low (read cycle)
t10 AS#, DS# rising edge to D[31:16] high impedance
Note
Hardware Functional Specification
Issue Date: 01/02/08
T
CLK
t1
t3
Hi-Z
t7
Hi-Z
Hi-Z

Figure 7-4: M68K #2 Timing (MC68030)

Table 7-4: M68K #2 Timing (MC68030)

Parameter
CLK may be turned off (held low) between accesses - see Section 13.5, "Turning Off
BCLK Between Accesses" on page 86
VALID
t4
VALID
t9
VALID
*
Page 31
t2
t6
t5
Hi-Z
t8
Hi-Z
t10
Hi-Z
Min Max Units
0 33 MHz
1/f
CLK
0 ns
0 ns
22 ns
18 ns
26 ns
T
CLK
T / 2
CLK
0 ns
0 ns
20 ns
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