Figure 7-11: Single Monochrome 4-Bit Panel A.c. Timing - Epson S1D13704 Technical Manual

Page 38
Sync Timing
Data Timing
Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
Symbol
t1 Frame Pulse setup to Line Pulse falling edge
t2 Frame Pulse hold from Line Pulse falling edge
t3 Line Pulse period
t4 Line Pulse pulse width
t5 MOD delay from Line Pulse rising edge
t6 Shift Pulse falling edge to Line Pulse rising edge
t7 Shift Pulse falling edge to Line Pulse falling edge
t8 Line Pulse falling edge to Shift Pulse falling edge
t9 Shift Pulse period
t10 Shift Pulse pulse width low
t11 Shift Pulse pulse width high
t12 FPDAT[7:4] setup to Shift Pulse falling edge
t13 FPDAT[7:4] hold to Shift Pulse falling edge
t14 Line Pulse falling edge to Shift Pulse rising edge
1. Ts = pixel clock period
2. t1 = t3 - 9Ts
min min
3. t3 = [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
min
4. t6 = [(REG[08h] bits 4-0) x 8 + 2]Ts
min
5. t7 = [(REG[08h] bits 4-0) x 8 + 11]Ts
min
S1D13704
X26A-A-001-04
Frame Pulse
Line Pulse
DRDY (MOD)
Line Pulse
Shift Pulse
FPDAT[7:4]

Figure 7-11: Single Monochrome 4-Bit Panel A.C. Timing

Parameter
t1
t4
t5
t6
t8
t14
t7
t12
*
Min
note 2
note 3
note 4
note 5
t14 + 2
Epson Research and Development
Vancouver Design Center
t2
t3
t9
t11 t10
t13
1 2
Typ Max
9
9
1
4
2
2
2
2
23
Hardware Functional Specification
Issue Date: 01/02/08
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts