Epson S1D13704 Technical Manual page 323

Epson Research and Development
Vancouver Design Center
A[25:0]
REG#
CE1#
CE2#
OE#
WAIT#
D[15:0]
A[25:0]
REG#
CE1#
CE2#
OE#
WE#
WAIT#
D[15:0]
Interfacing to the PC Card Bus
Issue Date: 01/02/12
During a read cycle, OE# (output enable) is driven low. A write cycle is specified by
driving OE# high and driving the write enable signal (WE#) low. The cycle can be
lengthened by driving WAIT# low for the time needed to complete the cycle.
Figure 2-1: and Figure 2-2: illustrate typical memory access cycles on the PC Card bus.
Hi-Z
Transfer Start
Figure 2-1: PC Card Read Cycle
Hi-Z
Transfer Start
Figure 2-2: PC Card Write Cycle
ADDRESS VALID
DATA VALID
Transfer Complete
*
ADDRESS VALID
DATA VALID
Transfer Complete
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Hi-Z
Hi-Z
S1D13704
X26A-G-009-03