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Page 16
6.5 Clock Input Support
6.6 LCD Panel Voltage Setting
6.7 Monochrome LCD Panel Support
6.8 Color Passive LCD Panel Support
6.9 Color TFT/D-TFD LCD Panel Support
S1D13704
X26A-G-005-03
The input clock (CLKI) frequency can be up to 50.0MHz for the S1D13704 if the internal
clock divide by 2 is set. If the clock divide is not used, the maximum CLKI frequency is
25MHz.
A 25.0MHz oscillator (U2, socketed) is provided as the default clock source.
The S5U13704B00C board supports both 3.3V and 5.0V LCD panels through the single
LCD connector J5. The voltage level is selected by setting jumper J4 to the appropriate
position. Refer to Table 2-3: "Jumper Settings," on page 9 for setting this jumper.
The S1D13704 directly supports 4 and 8-bit, dual and single, monochrome passive LCD
panels. All necessary signals are provided on the 40-pin ribbon cable header J5. The
interface signals on the cable are alternated with grounds to reduce crosstalk and noise.
Refer to Table 3-1: "LCD Signal Connector (J5) Pinout," on page 10 for specific
connection information.
The S1D13704 directly supports 4 and 8, dual and single, color passive LCD panels. All
the necessary signals are provided on the 40-pin ribbon cable header J5. The interface
signals on the cable are alternated with grounds to reduce crosstalk and noise.
Refer to Table 3-1: "LCD Signal Connector (J5) Pinout," on page 10 for specific
connection information.
The S1D13704 directly supports 9 and 12-bit active matrix color TFT/D-TFD panels. All
the necessary signals can also be found on the 40-pin LCD connector J5. The interface
signals on the cable are alternated with grounds to reduce crosstalk and noise.
Refer to Table 3-1: "LCD Signal Connector (J5) Pinout," on page 10 for connection infor-
mation.
*
S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/12
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