Table 8-8: Selection Of Swivelview Mode - Epson S1D13704 Technical Manual

Page 68
REG[1Ah] Scratch Pad Register
Address = FFFAh
Scratch bit 7 Scratch bit 6
bits 7-0
REG[1Bh] SwivelView Mode Register
Address = FFFBh
SwivelView SwivelView
Mode Enable Mode Select
bit 7
bit 6
bit 2
bits 1-0
S1D13704
X26A-A-001-04
Scratch bit 5 Scratch bit 4
Scratch Pad Register
This register contains general use read/write bits. These bits have no effect on hardware.
n/a n/a
SwivelView Mode Enable
When this bit = 1, SwivelView Mode is enabled. When this bit = 0, Landscape Mode is
enabled.
SwivelView Mode Select
When this bit = 0, Default SwivelView Mode is selected. When this bit = 1, Alternate
SwivelView Mode is selected. See Section 12, "SwivelView™" on page 79 for further
information on SwivelView Mode.
The following table shows the selection of SwivelView Mode.
SwivelView
Mode Enable
(REG[1Bh] bit 7)
0
1
1
reserved
reserved bits must be set to 0.
SwivelView Mode Pixel Clock Select Bits [1:0]
These two bits select the Pixel Clock (PCLK) source in SwivelView Mode - these bits
have no effect in Landscape Mode. The following table shows the selection of PCLK and
MCLK in SwivelView Mode - see Section 12, "SwivelView™" on page 79 for details.
Scratch bit 3 Scratch bit 2
n/a
*

Table 8-8: Selection of SwivelView Mode

SwivelView
Mode Select
(REG[1Bh] bit 6)
X
0
1
Epson Research and Development
Vancouver Design Center
Scratch bit 1
SwivelView
Mode Pixel
reserved
Clock Select
Bit 1
Mode
Landscape
Default SwivelView
Alternate SwivelView
Hardware Functional Specification
Issue Date: 01/02/08
Read/Write
Scratch bit 0
Read/Write
SwivelView
Mode Pixel
Clock Select
Bit 0