Cpu/Bus Interface Header Strips - Epson S1D13704 Technical Manual

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6.13 CPU/Bus Interface Header Strips

S1D13704
X26A-G-005-03
All of the CPU/Bus interface pins of the S1D13704 are connected to the header strips H1
and H2 for easy interface to a CPU/Bus other than ISA.
Refer to Table 4-1: "CPU/BUS Connector (H1) Pinout," on page 11 and Table 4-2:
"CPU/BUS Connector (H2) Pinout," on page 12 for specific settings.
Note
These headers only provide the CPU/Bus interface signals from the S1D13704. When
another host bus interface is selected by CNF[3:0] and BS#, appropriate external decode
logic MUST be used to access the S1D13704. Refer to Table 5-1: "Host Bus Interface
Pin Mapping," on page 13 for connection details.
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S5U13704B00C Rev. 1.0 ISA Bus Evaluation Board User Manual
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/12