Power Down/Up Timing; Table 7-8: Power Down/Up Timing; Figure 7-9: Power Down/Up Timing - Epson S1D13704 Technical Manual

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7.3.2 Power Down/Up Timing

LCDPWR Override
(REG[03h] bit 3)
HW Power Save
or
Software Power Save
REG[03h] bits [1:0]
FP Signals
LCDPWR
(polarity set by CNF4)
Symbol
HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
t1
inactive - LCDPWR Override = 1
HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
t2
active - LCDPWR Override = 1
HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
t3
inactive - LCDPWR Override = 0
LCDPWR low to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY inactive
t4
- LCDPWR Override = 0
HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY,
t5
LCDPWR active - LCDPWR Override = 0
t6 LCDPWR Override active (1) to LCDPWR inactive
t7 LCDPWR Override inactive (1) to LCDPWR active
S1D13704
X26A-A-001-04
11 00
Active Inactive
t4
t3
Active Inactive

Figure 7-9: Power Down/Up Timing

Table 7-8: Power Down/Up Timing

Parameter
11
Active
t5
t6
Active
*
Epson Research and Development
Vancouver Design Center
00 11
t2
t1
Inactive Active
Inactive Active
Min Typ Max
1
1
1
127
0
1
1
Hardware Functional Specification
Issue Date: 01/02/08
t7
Units
Frame
Frame
Frame
Frame
Frame
Frame
Frame