Epson S1D13704 Technical Manual page 301

Epson Research and Development
Vancouver Design Center
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4-2: Host Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2-1: NEC VR4102 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4-1: Typical Implementation of VR4102 to S1D13704 Interface . . . . . . . . . . . . . . . . 13
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 01/02/12
List of Tables
List of Figures
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Page 5
S1D13704
X26A-G-008-05