Mcf5307 To S1D13704 Interface; Hardware Description - Epson S1D13704 Technical Manual

Epson Research and Development
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4 MCF5307 To S1D13704 Interface

4.1 Hardware Description

Figure 4-1: Typical Implementation of MCF5307 to S1D13704 Interface
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 01/02/12
The S1D13704 is interfaced to the MCF5307 with a minimal amount of glue logic. One
inverter is required to change the polarity of the WAIT# signal, which is an active low
signal to insert wait states in the bus cycle, while the MCF5307's Transfer Acknowledge
signal (TA) is an active low signal to end the current bus cycle. The inverter is enabled by
CS# so that TA is not driven by the S1D13704 during non-S1D13704 bus cycles. A single
resistor is used to speed up the rise time of the WAIT# (TA) signal when terminating the
bus cycle.
The following diagram shows a typical implementation of the MCF5307 to S1D13704
interface.
MCF5307
A[16:31]
D[0:15]
CS4
TA
WE3
WE2
OE
BCLK0
RESET
*
Vcc
470
S1D13704
AB[15:0]
DB[15:0]
CS#
WAIT#
WE1#
WE0#
RD/WR#
RD#
BUSCLK
RESET#
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S1D13704
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