Using The Generic #1 Host Bus Interface - Epson S1D13704 Technical Manual

Epson Research and Development
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4.1.2 Using The Generic #1 Host Bus Interface

Figure 4-2: Typical Implementation of MC68328 to S1D13704 Interface - Generic #1
Interfacing to the Motorola MC68328 'Dragonball' Microprocessor
Issue Date: 01/02/12
If UDS and/or LDS are required for their alternate IO functions, then the MC68328 to
S1D13704 interface may be implemented using the S1D13704 Generic #1 host bus
interface. Note that in either case, the DTACK signal must be made available for the
S1D13704, since it inserts a variable number of wait states depending upon CPU/LCD
synchronization and the LCD panel display mode. WAIT# must be inverted (using an
inverter enabled by CS#) to make it an active high signal and thus compatible with the
MC68328 architecture. A single resistor is used to speed up the rise time of the WAIT#
(DTACK) signal when
terminating the bus cycle.
The following diagram shows a typical implementation of the MC68328 to S1D13704
using the Generic #1 host bus interface.
MC68328
A[15:0]
D[15:0]
CSB3
DTACK
UWE
LWE
OE
CLK0
RESET
S1D13704
AB[15:0]
DB[15:0]
CS#
Vcc
*
470
WAIT#
WE1#
WE0#
RD/WR#
RD#
BUSCLK
RESET#
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