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EPSON Research and Development
Vancouver Design Center
Table 3-1:
S1D13704/5 Configuration for Generic #2 Bus Interface . . . . . . . . . . . . . . . . . . . . . . 11
Table 3-2:
S1D13704/5 Generic #2 Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3-1:
S1D13704 to TMPR3912/22U Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
S5U13704/5 - TMPR3912/22U CPU Module
Issue Date: 01/03/07
List of Tables
List of Figures
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Page 5
X00A-G-004-02
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