Test Software - Epson S1D13704 Technical Manual

Page 20

4.5 Test Software

BR4 equ
OR4 equ
MemStart equ
address
RevCodeReg equ
ter
Start mfspr
registers
andis.
andis.
oris
ori
enable
stw
andis.
oris
bits
ori
clock;
stw
andis.
oris
mem space
Loop lbz
b
end
S1D13704
X26A-G-010-03
The test software to exercise this interface is very simple. It configures chip select 4 on the
MPC821 to map the S1D13704 to an unused 64k byte block of address space and loads the
appropriate values into the option register for CS4. At that point the software runs in a tight
loop reading the 13704 Revision Code Register REG[00h], which allows monitoring of the
bus timing on a logic analyzer.
The source code for this test routine is as follows:
$120
$124
$40
FFE0
r1,IMMR
r1,r1,$ffff
r2,r0,0
r2,r2,MemStart
r2,r2,$0801
r2,BR4(r1)
r2,r0,0
r2,r2,$ffc0
r2,r2,$0708
r2,OR4(r1)
r1,r0,0
r1,r1,MemStart
r0,RevCodeReg(r1) ; read revision code into r1
Loop
; CS4 base register
; CS4 option register
; upper word of S1D13704 start
; address of Revision Code Regis-
; get base address of internal
; clear lower 16 bits to 0
; clear r2
; write base address
; port size 16 bits; select GPCM;
; write value to base register
; clear r2
*
; address mask – use upper 10
; normal CS negation; delay CS ½
; inhibit burst
; write to option register
; clear r1
; point r1 to start of S1D13704
; branch forever
Interfacing to the Motorola MPC821 Microprocessor
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/12