Clock Input; Miscellaneous; Power Supply - Epson S1D13704 Technical Manual

Epson Research and Development
Vancouver Design Center
Pin Name Type
FPLINE O
FPSHIFT O
LCDPWR O
DRDY O

5.2.3 Clock Input

Pin Name
CLKI

5.2.4 Miscellaneous

Pin Name Type
CNF[4:0] I
I/O,
GPIO0
I
TESTEN I

5.2.5 Power Supply

Pin Name
COREVDD
IOVDD
VSS
Hardware Functional Specification
Issue Date: 01/02/08
RESET#
Pin # Cell
State
38 CN3
28 CN3
0 if CNF4 = 1
43 CO1
1 if CNF4 = 0
42 CN3
Type Pin # Driver
I 51 C
RESET#
Pin # Cell
State
45, 46, 47, As set by
C
48, 49 hardware
CS/
22 Input
TS1
High
44 CD
Impedance
Type Pin # Driver
1, 21, 41,
P P
61
P 10, 29, 52 P
20, 27, 40,
P 50, 60, 72, P
80
0 Line Pulse
0 Shift Clock
LCD Power Control
This pin has multiple functions.
• TFT/D-TFD Display Enable (DRDY).
0 • LCD Backplane Bias (MOD).
• Second Shift Clock (FPSHIFT2).
See "LCD Interface Pin Mapping" for summary.
Input Clock
These inputs are used to configure the S1D13704 - see
*
"Summary of Configuration Options".
Must be connected directly to IO V
This pin has multiple functions - see REG[03h] bit 2.
• General Purpose Input/Output pin.
• Hardware Power Save.
Test Enable input. This input must be connected to V
Core V
DD
IO V
DD
Common V
SS
Description
Description
Description
or V .
DD SS
Description
X26A-A-001-04
Page 21
.
SS
S1D13704