Table 8-2: Gray Shade/Color Mode Selection; Table 8-3: High Performance Selection - Epson S1D13704 Technical Manual

Page 56
REG[02h] Mode Register 1
Address = FFE2h
Bit-Per-Pixel Bit-Per-Pixel
Bit 1 Bit 0
bits 7-6
bit 5
S1D13704
X26A-A-001-04
Input Clock
High
divide
Performance
(CLKI/2)
Bit-Per-Pixel Bits [1:0]
These bits select the color or gray-shade depth (Display Mode).

Table 8-2: Gray Shade/Color Mode Selection

Color/Mono Bit-Per-Pixel Bit 1
REG[01h] bit 6 REG[02h] bit 7
0
1
High Performance (Landscape Modes Only)
When this bit = 0, the internal Memory clock (MCLK) is a divided-down version of the
Pixel clock (PCLK). The denominator is dependent on the bit-per-pixel mode - see the
table below.

Table 8-3: High Performance Selection

High Performance BPP Bit 1
0
1
When this bit = 1, MCLK is fixed to the same frequency as PCLK for all bit-per-pixel
modes. This provides a faster screen update performance in 1, 2, 4 bit-per-pixel modes, but
also increases power consumption. This bit can be set to 1 just before a major screen
update, then set back to 0 to save power after the update. This bit has no effect in Swivel-
View mode. Refer to REG[1Bh] SwivelView Mode Register on page 68 for SwivelView
mode clock selection.
Display Blank
Bit-Per-Pixel Bit 0
REG[02h] bit 6
0
0
1
0
1
1
0
0
1
0
1
1
*
BPP Bit 0
0
0
1
0
1
1
X X
Epson Research and Development
Vancouver Design Center
Hardware
Frame
Video Invert
Repeat
Enable
Display Mode
2 Gray shade
4 Gray shade
16 Gray shade
reserved
2 Colors
4 Colors
16 Colors
256 Colors
Display Modes
MClk = PClk/8 1 bit-per-pixel
MClk = PClk/4 2 bit-per-pixel
MClk = PClk/2 4 bit-per-pixel
MClk = PClk 8 bit-per-pixel
MClk = PClk
Hardware Functional Specification
Issue Date: 01/02/08
Read/Write.
Software
Video Invert
1 bit-per-pixel
2 bit-per-pixel
4 bit-per-pixel
1 bit-per-pixel
2 bit-per-pixel
4 bit-per-pixel
8 bit-per-pixel